US 12,322,439 B2
Neuromorphic memory circuit and operating method therof
Sangbum Kim, Seoul (KR); Uicheol Shin, Seoul (KR); and Suyeon Jang, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and SNU R&DB FOUNDATION, Seoul (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and SNU R&DB FOUNDATION, Seoul (KR)
Filed on Mar. 21, 2022, as Appl. No. 17/699,756.
Claims priority of application No. 10-2021-0137460 (KR), filed on Oct. 15, 2021.
Prior Publication US 2023/0119915 A1, Apr. 20, 2023
Int. Cl. G11C 13/00 (2006.01); G11C 11/54 (2006.01)
CPC G11C 11/54 (2013.01) [G11C 13/003 (2013.01); G11C 13/0061 (2013.01); G11C 13/0004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neuromorphic memory circuit comprising:
a plurality of memory cells,
wherein each of the plurality of memory cells comprises:
a first switching element configured to have a threshold switching time determined based on a voltage applied to both ends of the first switching element at a time of receiving an input signal, and to output the input signal in response to an elapse of the threshold switching time from a point in time at which the input signal is received;
a first resistive memory element connected to the first switching element and configured to divide the voltage applied to both ends of the first switching element;
a synapse circuit configured to generate an output signal in response to the input signal delayed by the threshold switching time; and
a capacitor connected to an output of the synapse circuit.