US 12,322,438 B2
Latch circuit formed by modified memory cells
Hua-Hsin Yu, Hsinchu (TW); Cheng Hung Lee, Hsinchu (TW); Hung-Jen Liao, Hsinchu (TW); and Hau-Tai Shieh, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 26, 2024, as Appl. No. 18/424,413.
Application 18/424,413 is a continuation of application No. 17/201,636, filed on Mar. 15, 2021, granted, now 11,915,743.
Application 17/201,636 is a continuation of application No. 16/507,805, filed on Jul. 10, 2019, granted, now 10,950,296, issued on Mar. 16, 2021.
Claims priority of provisional application 62/698,865, filed on Jul. 16, 2018.
Prior Publication US 2024/0170053 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/412 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/412 (2013.01) [G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a latch circuit, comprising:
providing a first memory cell comprising:
a word line;
first and second bit lines;
first and second inverters, the first inverter having an output directly connected to an input of the second inverter by a first cross-coupling line, the second inverter having an output directly connected to an input of the first inverter by a second cross-coupling line;
a first pass gate transistor coupled between the first bit line and the output of the second inverter and having a gate coupled to the word line; and
a second pass gate transistor coupled between the second bit line and the output of the first inverter and having a gate coupled to the word line;
providing a second memory cell comprising:
the word line;
the first and second bit lines;
third and fourth inverters, the third inverter having an output directly connected to an input of the fourth inverter by a third cross-coupling line, the fourth inverter having an output directly connected to an input of the third inverter by a fourth cross-coupling line;
a third pass gate transistor coupled between the first bit line and the output of the fourth inverter and having a gate coupled to the word line; and
a fourth pass gate transistor coupled between the second bit line and the output of the third inverter and having a gate coupled to the word line;
cutting the second cross-coupling line to decouple the output of the second inverter from the input of the first inverter;
cutting the third cross-coupling line to decouple the output of the third inverter from the input of the fourth inverter;
directly coupling the output of the first inverter to the second bit line by a first coupling line;
directly coupling the output of the fourth inverter to the first bit line by a second coupling line;
directly coupling the input of the first inverter to ground by a third coupling line;
directly coupling the input of the fourth inverter to ground by a fourth coupling line;
decoupling one side of the first inverter and one side of the fourth inverter from power; and
coupling the word line to receive a clock signal.