US 12,322,437 B2
Memory chip and memory system including the same
Kwangsook Noh, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 24, 2023, as Appl. No. 18/189,756.
Claims priority of application No. 10-2022-0076632 (KR), filed on Jun. 23, 2022.
Prior Publication US 2023/0420039 A1, Dec. 28, 2023
Int. Cl. G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 11/00 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/005 (2013.01); G11C 11/408 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory chip comprising:
a plurality of storage blocks respectively including a plurality of memory cells; and
a logic circuit configured to control the plurality of storage blocks,
wherein the logic circuit includes
an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks, wherein the logic circuit is further configured to
allocate block address codes having a bit inversion relationship with each other, to a storage block having a kth longest distance from the input/output pad among the plurality of storage blocks and a storage block having a kth shortest distance from the input/output pad among the plurality of storage blocks, where k is a natural number, among the plurality of storage blocks,
output a mode selection signal in response to external control,
output an external address code received together with an access command in response to the mode selection signal indicating a first addressing mode, and output a first address code having the bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and
select a first storage block to be controlled by the access command from among the plurality of storage blocks, based on the external address code or the first address code.