US 12,322,435 B2
Sense amplifier with read circuit for compute-in-memory
Chieh Lee, Hsinchu (TW); Chia-En Huang, Hsinchu County (TW); Yi-Ching Liu, Hsinchu (TW); Wen-Chang Cheng, Richmond, TX (US); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 11, 2022, as Appl. No. 17/692,996.
Claims priority of provisional application 63/224,927, filed on Jul. 23, 2021.
Prior Publication US 2023/0023505 A1, Jan. 26, 2023
Int. Cl. G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 5/063 (2013.01); G11C 7/06 (2013.01); G11C 7/062 (2013.01); G11C 7/065 (2013.01); G11C 7/1078 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 7/1051 (2013.01); G11C 11/4093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array configured to store data;
a sense amplifier circuit coupled to the memory array and having a bit line and an inverted bit line;
a first read circuit connected to one of the bit line and the inverted bit line of the sense amplifier circuit, wherein the first read circuit includes a first input that receives a read column select signal for activating the first read circuit to read the data out of the memory array through the first read circuit during a read operation; and
a load balancing transistor having a gate connected to the other one of the bit line and the inverted bit line and a drain/source path that has each side of the drain/source path connected to a reference,
wherein the other one of the bit line and the inverted bit line is connected to the gate of the load balancing transistor without being connected to a second read circuit and without being connected to another load balancing transistor.