| CPC G11C 11/4078 (2013.01) [G11C 11/40615 (2013.01); G11C 11/40622 (2013.01)] | 19 Claims |
|
1. A memory controller for generating accesses for a memory, comprising:
a row hammer logic circuit for providing a sample request;
wherein in response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row; and
in response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory; and
a leaky-bucket mitigation counter that increments a mitigation count value for a first row in response to the memory controller generating the mitigation command for the first row, decrements the mitigation count value periodically, and stalls an issuance of mitigation commands to the first row in response to the mitigation count value exceeding a mitigation count limit.
|