US 12,322,433 B2
Power and performance optimization in a memory subsystem
Vijay Anand Mathiyalagan, Barasat (IN); and Sambaran Mitra, Chennai (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/131,585.
Prior Publication US 2022/0199142 A1, Jun. 23, 2022
Int. Cl. G11C 11/4074 (2006.01); G06F 11/10 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4074 (2013.01) [G06F 11/1004 (2013.01); G11C 11/4096 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory controller;
a memory Input/Output (IO) physical layer coupled to the memory controller; and
a voltage supply generator coupled to the memory IO physical layer, wherein the voltage supply generator is to provide an adjustable voltage supply to the memory IO physical layer, wherein the memory controller is to instruct the voltage supply generator directly or indirectly to change the adjustable voltage supply and enable or disable an error detection mechanism used to detect errors in data conveyed over a data link that couples the memory IO physical layer to a memory according to noise level on the data link that couples the memory IO physical layer to the memory and based on a determination to either emphasize power conservation or to maintain performance.