US 12,322,431 B2
Refresh address generation circuit and method, memory, and electronic device
Yinchuan Gu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 9, 2023, as Appl. No. 18/332,706.
Application 18/332,706 is a continuation of application No. PCT/CN2022/129530, filed on Nov. 3, 2022.
Claims priority of application No. 202210601863.9 (CN), filed on May 30, 2022.
Prior Publication US 2023/0386546 A1, Nov. 30, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 8/18 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/406 (2013.01) [G11C 11/40611 (2013.01); G11C 8/18 (2013.01); G11C 11/40618 (2013.01); G11C 11/408 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A refresh address generation circuit, comprising:
a refresh control circuit, configured to sequentially receive a plurality of first refresh commands, and perform first refresh operations respectively; and further configured to: under a condition that a number of the first refresh operations is less than a preset value, output a first clock signal; and under a condition that the number of the first refresh operations is equal to the preset value n, output a second clock signal, wherein n is a positive integer greater than or equal to 1; and
an address generator, coupled to the refresh control circuit, and configured to pre-store a first address and to receive the first clock signal or the second clock signal, wherein the address generator is further configured to: output a first to-be-refreshed address in response to the first clock signal during each of the first refresh operations, wherein the first to-be-refreshed address comprises the first address; and change the first address in response to the second clock signal.