US 12,322,430 B2
Refresh circuit and memory
Xianlei Cao, Hefei (CN); and Xian Fan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 8, 2023, as Appl. No. 18/331,923.
Application 18/331,923 is a continuation of application No. PCT/CN2022/079803, filed on Mar. 8, 2022.
Claims priority of application No. 202210044510.3 (CN), filed on Jan. 14, 2022.
Prior Publication US 2023/0317133 A1, Oct. 5, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/406 (2013.01) [G11C 11/4085 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A refresh circuit, comprising:
a preprocessing module, configured to receive a word line activation command and a clock signal, count clock signals in response to the word line activation command, and output a word line address corresponding to a current word line activation command as a word line address signal when a count value of the clock signals reaches a preset value;
an address processing module, connected with the preprocessing module, and configured to count all received word line address signals, and output a word line address signal with a largest number of occurrence times as a row hammer address;
a first processing unit, connected with the address processing module, and configured to generate a first supplementary refresh address and a second supplementary refresh address according to the row hammer address received, wherein a word line to which the first supplementary refresh address points and a word line to which the second supplementary refresh address points are adjacent to a word line to which the row hammer address points;
a second processing unit, configured to generate a normal refresh address according to a refresh command;
a refresh unit, connected with the first processing unit and the second processing unit, and configured to perform a refresh operation according to an acquired address signal; and
a control unit, connected with the first processing unit and the second processing unit, and configured to select to output the normal refresh address, the first supplementary refresh address or the second supplementary refresh address; or connected with the refresh unit, and configured to control the refresh unit to select to receive the normal refresh address, the first supplementary refresh address or the second supplementary refresh address.