| CPC G09G 3/3685 (2013.01) [G09G 3/3275 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/0297 (2013.01); G09G 2370/10 (2013.01)] | 18 Claims |
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1. A source driver integrated circuit (IC) comprising:
a first latch circuit configured to sample image data;
a second latch circuit configured to output the sampled image data according to a latch enable signal;
a latch enable signal output control circuit configured to output the latch enable signal at a first timing or at a second timing different from the first timing according to a timing setting signal;
a digital-to-analog converter configured to convert the image data output from the second latch circuit into an analog data voltage;
an output buffer circuit configured to amplify and output the data voltage according to the latch enable signal; and
a multiplexer (Mux) circuit configured to be turned on during a period of a first level of a source output enable signal to output the data voltage output from the output buffer circuit to each of a plurality of channels,
wherein the timing setting signal contains a flag having one of a first value or a second value,
wherein the latch enable signal output control circuit is configured to output the latch enable signal at the first timing when the timing setting signal having the first value is received, and output the latch enable signal at the second timing when the timing setting signal having the second value is received, and
wherein the flag is set to the first value or the second value based on a comparison between a noise of the digital-to-analog converter and a noise of the Mux circuit.
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