US 12,322,336 B2
Pixel driving circuit and display apparatus
Wenhui Gao, Beijing (CN); Dan Cao, Beijing (CN); Yonglin Guo, Beijing (CN); Jingwen Zhang, Beijing (CN); and Zhiliang Jiang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/293,172
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jan. 19, 2023, PCT No. PCT/CN2023/073090
§ 371(c)(1), (2) Date Jan. 29, 2024,
PCT Pub. No. WO2024/152289, PCT Pub. Date Jul. 25, 2024.
Prior Publication US 2025/0078748 A1, Mar. 6, 2025
Int. Cl. G09G 3/3233 (2016.01); G09G 3/32 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0248 (2013.01); G09G 2310/061 (2013.01); G09G 2320/045 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A pixel driving circuit, comprising:
a driving transistor;
a storage capacitor having a first capacitor electrode and a second capacitor electrode;
a coupling capacitor having a third capacitor electrode and a fourth capacitor electrode;
a control transistor;
a data write transistor having a gate electrode connected to a gate line, a first electrode connected to a data line, and a second electrode connected a first electrode of the control transistor; and
a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor;
wherein the control transistor has a gate electrode connected to a fourth control signal line, a first electrode connected to the second electrode of the data write transistor, and a second electrode connected to the first capacitor electrode and the fourth capacitor electrode;
a gate electrode of the driving transistor is connected to the third capacitor electrode; and
the control transistor is an n-type transistor;
wherein the compensating transistor is an n-type transistor; and
the first control signal line and the fourth control signal line are connected to a same scan circuit, and are configured to receive output signals of different stages, respectively, from the same scan circuit.