US 12,322,331 B2
Display substrate and display apparatus
Yuzhen Guo, Beijing (CN); Zhenyu Zhang, Beijing (CN); Lubin Shi, Beijing (CN); Zhen Zhang, Beijing (CN); Chenyang Zhang, Beijing (CN); and Fuqiang Li, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/794,625
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 23, 2021, PCT No. PCT/CN2021/120001
§ 371(c)(1), (2) Date Mar. 30, 2023,
PCT Pub. No. WO2023/044680, PCT Pub. Date Mar. 30, 2023.
Prior Publication US 2024/0203343 A1, Jun. 20, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); H10K 59/131 (2023.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); H10K 59/131 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising: a display region and a non-display region, the display region is provided with M1 rows and N1 columns of pixel circuits and M2 rows and N2 columns of light emitting units, each light emitting unit comprises: a first light emitting device, a second light emitting device, and a third light emitting device, wherein the first light emitting device, the second light emitting device, and the third light emitting device emit light of different colors; wherein M1≠M2, N1≠N2;
each pixel circuit is connected with K light emitting devices emitting light of a same color, wherein K is a positive integer greater than or equal to 2;
each pixel circuit comprises a current control sub-circuit and a light emitting selection sub-circuit;
the current control sub-circuit is respectively connected with a reset signal terminal, an initial signal terminal, a scan signal terminal, a data signal terminal, a light emitting control terminal, a first power supply terminal, and a first node, and is configured to provide a drive current to the first node under control of the reset signal terminal, the initial signal terminal, the scan signal terminal, the data signal terminal, the light emitting control terminal, and the first power supply terminal;
the light emitting selection sub-circuit is respectively connected with the first node, K light emitting selection signal terminals, and the K light emitting devices emitting light of the same color, and is configured to sequentially provide a signal of the first node to the K light emitting devices emitting light of the same color under control of the K light emitting selection signal terminals,
wherein the display substrate further comprises: N1 columns of data signal lines, M1rows of scan signal lines, MI rows of first power supply lines, M1 rows of reset signal lines, M1 rows of initial signal lines, P rows of first light emitting selection signal lines, P rows of second light emitting selection signal lines, P rows of third light emitting selection signal lines, P rows of fourth light emitting selection signal lines, and P rows of light emitting control lines, P=M1 or M1/2;
the data signal lines extend along a first direction, and the scan signal lines, the first power supply lines, the reset signal lines, the initial signal lines, the first light emitting selection signal lines, the second light emitting selection signal lines, the third light emitting selection signal lines, the fourth light emitting selection signal lines, and the light emitting control lines extend along a second direction, wherein the first direction and the second direction intersect;
a scan signal line of an s-th row is connected with a scan signal terminal of a pixel circuit of an s-th row, a first power supply line of an s-th row is connected with a first power supply terminal of the pixel circuit of the s-th row, a reset signal line of an s-th row is connected with a reset signal terminal of the pixel circuit of the s-th row, an initial signal line of an s-th row is connected with an initial signal terminal of the pixel circuit of the s-th row, a data signal line of a t-th column is connected with a data signal terminal of a pixel circuit of a t-th column, 1≤s≤M1, 1≤t≤N1.