US 12,322,313 B2
Driving circuit, driving module, driving method and display device
Longfei Fan, Beijing (CN); and Pengcheng Lu, Beijing (CN)
Assigned to Yunnan Invensight Optoelectronics Technology Co., Ltd., Yunnan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/926,959
Filed by Yunnan Invensight Optoelectronics Technology Co., Ltd., Yunnan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Nov. 23, 2021, PCT No. PCT/CN2021/132572
§ 371(c)(1), (2) Date Nov. 21, 2022,
PCT Pub. No. WO2023/092304, PCT Pub. Date Jun. 1, 2023.
Prior Publication US 2024/0242649 A1, Jul. 18, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/20 (2013.01) [G09G 2300/0852 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A driving circuit, comprising a driving signal output terminal, a first node control circuit, an on-off control circuit and a first output circuit;
the first node control circuit is respectively electrically connected to a first control terminal, a first voltage terminal, a first node, a second input control terminal and a first clock signal terminal, and is configured to control to connect or disconnect the first node and the first voltage terminal under the control of a first control signal provided by the first control terminal, and control to connect or disconnect the first node and the first voltage terminal under the control of a first clock signal provided by the first clock signal terminal; the first control terminal is different from the first clock signal terminal;
the on-off control circuit is electrically connected to a second voltage terminal, the first node and a first output control terminal respectively, and is configured to control to connect or disconnect the first node and the first output control terminal under the control of a second voltage signal provided by the second voltage terminal;
the first output circuit is electrically connected to the first output control terminal, the first clock signal terminal and the driving signal output terminal respectively, and is configured to control to connect or disconnect the driving signal output terminal and the first clock signal terminal under the control of a potential of the first output control terminal;
wherein the driving circuit further comprises a second output control terminal control circuit and a second output circuit; wherein
the second output control terminal control circuit is electrically connected to the first node, a second output control terminal, a second clock signal terminal and the second voltage terminal respectively, and is configured to control to connect or disconnect the second output control terminal and the second clock signal terminal under the control of a potential of the first node, control to connect or disconnect the second output control terminal and the second voltage terminal under the control of a second clock signal provided by the second clock signal terminal;
the second output circuit is respectively electrically connected to the second output control terminal, the first voltage terminal and the driving signal output terminal, and is configured to control to connect or disconnect the driving signal output terminal and the first voltage terminal under the control of a potential of the second output control terminal;
wherein the first control terminal is not connected directly to the second output control terminal, and the first control terminal is connected to the second output control terminal via the first node control circuit and the second output control terminal control circuit.