| CPC G09G 3/006 (2013.01) [G11C 19/287 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01)] | 14 Claims |

|
1. A gate drive circuit, comprising:
multiple cascaded shift registers, wherein each of the shift registers comprises a scan output terminal and a pull-down module; in each of the shift registers, the scan output terminal is electrically connected to a scan signal line, and the pull-down module is configured to transmit a voltage of a power node to the scan output terminal when the pull-down module is turned on;
wherein in each of the shift registers located in odd-numbered rows, the power node is electrically connected to a first detection signal line, while in each of the shift registers located in even-numbered rows, the power node is electrically connected to a second detection signal line;
when the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line are configured to transmit a first voltage to the corresponding scan signal lines when the respective pull-down modules are turned on; when the gate drive circuit is in a detection state, the pull-down modules are turned on, and the first detection signal line and the second detection signal line transmit a second voltage to the corresponding scan signal lines; the second voltage is greater than the first voltage; and if it is detected that a resistance between the first detection signal line and the second detection signal line is lower than in the driving state, it is determined that a short circuit occurs in the gate drive circuit.
|