US 12,321,867 B2
Finite automata global counter in a data flow graph-driven analytics platform having analytics hardware accelerators
Rajan Goyal, Saratoga, CA (US); and Satyanarayana Lakshmipathi Billa, Sunnyvale, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jan. 11, 2024, as Appl. No. 18/410,299.
Application 18/410,299 is a continuation of application No. 16/825,714, filed on Mar. 20, 2020, granted, now 11,934,964.
Prior Publication US 2024/0160964 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 17/00 (2019.01); G06F 7/00 (2006.01); G06F 16/2455 (2019.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01)
CPC G06N 5/04 (2013.01) [G06F 16/24568 (2019.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a memory including a finite automata (FA) graph, wherein the FA graph includes a plurality of nodes connected by directional arcs, the plurality of nodes including a skip node capable of processing bytes remaining in a payload; and
one or more hardware-based regular expression (RegEx) accelerators connected to the memory, wherein each RegEx accelerator includes a regular expression engine, the regular expression engine configured to perform a regular expression operation on the payload.