US 12,321,857 B2
Methods and apparatus to perform machine-learning model operations on sparse accelerators
Martin Power, Dublin (IE); Kevin Brady, Newry (GB); Niall Hanrahan, Galway (IE); Martin-Thomas Grymel, Leixlip (IE); David Bernard, Kilcullen (IE); and Gary Baugh, Bray (IE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,924.
Prior Publication US 2021/0319317 A1, Oct. 14, 2021
Int. Cl. G06F 17/15 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/08 (2013.01) [G06F 17/15 (2013.01); G06F 17/153 (2013.01); G06N 3/063 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
first circuitry comprising one or more multiply accumulators;
a buffer to store first sparsity data, the first sparsity data indicating sparsity in input data of a first convolution type;
second circuitry to generate second sparsity data for a second convolution type;
one or more other buffers to store input data of a convolution; and
third circuitry to:
select sparsity data between the first sparsity data and the second sparsity data based on a type of a convolution,
identify one or more data elements in the input data of the convolution based on the selected sparsity data, and
transfer the one or more data elements from the one or more other data buffers to the first circuitry,
wherein the first circuitry is to execute at least part of the convolution by performing one or more multiply-accumulate operations on the one or more data elements.