	US 12,321,848 B2
	Signal processing circuit, signal processing device, and signal processing method using logic circuit
Akito Sekiya, Kanagawa (JP); Tomohiro Matsumoto, Kanagawa (JP); Hiroyuki Yamagishi, Kanagawa (JP); Yasushi Fujinami, Kanagawa (JP); Yusuke Oike, Kanagawa (JP); and Ryoji Ikegaya, Kanagawa (JP)
Assigned to SONY CORPORATION, Tokyo (JP)
Appl. No. 17/250,310
Filed by SONY CORPORATION, Tokyo (JP)
PCT Filed Jul. 5, 2019, PCT No. PCT/JP2019/026912 § 371(c)(1), (2) Date Dec. 31, 2020, PCT Pub. No. WO2020/013101, PCT Pub. Date Jan. 16, 2020.
Claims priority of application No. 2018-130692 (JP), filed on Jul. 10, 2018.
Prior Publication US 2021/0376836 A1, Dec. 2, 2021
Int. Cl. H03K 19/20 (2006.01); G06N 3/048 (2023.01)

CPC G06N 3/048 (2023.01) [H03K 19/20 (2013.01)]

13 Claims

1. A signal processing circuit, comprising:

a first logic circuit configured to:

output, in a case where a first timing of a period is one of earlier or same as a second timing of the period, a first output signal at the first timing and a second output signal at the second timing, wherein

the first timing of the period corresponds to a timing at which a first input signal changes from a first state to a second state,

the second timing of the period corresponds to a timing at which a second input signal changes from a third state to a fourth state,

the first input signal is associated with the first output signal, and

the second input signal is associated with the second output signal; and

output, in a case where the first timing of the period is later than the second timing of the period, each of the first output signal and the second output signal at the second timing.