US 12,321,775 B2
Interrupt handling by migrating interrupts between processing cores
Sampath Malalangaradass, Bangalore (IN)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 21, 2021, as Appl. No. 17/481,069.
Prior Publication US 2023/0100059 A1, Mar. 30, 2023
Int. Cl. G06F 9/48 (2006.01); G06F 13/24 (2006.01)
CPC G06F 9/4812 (2013.01) [G06F 13/24 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of processing cores; and
an interrupt controller, comprising:
an input terminal configured to receive an interrupt request;
an interrupt controller timer;
an output terminal configured to output an interrupt signal based on the interrupt request, wherein the interrupt signal is configured to cause a first processing core of the plurality of processing cores to service an interrupt corresponding to the interrupt signal;
interface configuration and status circuitry configured to track a period of time that the interrupt signal is transmitted to the first processing core; and
an interrupt wait threshold register that stores a wait threshold, wherein the interrupt controller is configured to compare the period of time to the wait threshold and to output an additional interrupt signal to a second processing core of the plurality of processing cores when the period of time exceeds the wait threshold, and the additional interrupt signal is configured to cause the second processing core to service the interrupt.