US 12,321,750 B2
Entering protected pipeline mode with clearing
Timothy D. Anderson, University Park, TX (US); Joseph Zbiciak, San Jose, CA (US); Duc Bui, Grand Prairie, TX (US); Mel Alan Phipps, Sugar Land, TX (US); and Todd T. Hahn, Sugar Land, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 28, 2021, as Appl. No. 17/360,646.
Application 15/429,205 is a division of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Application 17/360,646 is a continuation of application No. 16/384,537, filed on Apr. 15, 2019, granted, now 11,048,513.
Application 16/384,537 is a continuation in part of application No. 16/227,238, filed on Dec. 20, 2018, granted, now 11,036,648.
Application 16/227,238 is a continuation of application No. 15/429,205, filed on Feb. 10, 2017, granted, now 10,162,641, issued on Dec. 25, 2018.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2021/0326136 A1, Oct. 21, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 9/3016 (2013.01) [G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/383 (2013.01); G06F 9/3867 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an instruction execution pipeline having a plurality of pipeline stages and configured to operate in an unprotected mode and a protected mode; and
pipeline control circuitry configured to:
cause the instruction execution pipeline to begin execution of an unprotected instruction in the unprotected mode; and
during the execution of the unprotected instruction:
based on a mode change instruction that specifies a change from the unprotected mode to the protected mode, cause the instruction execution pipeline to operate in the protected mode;
determine whether the mode change instruction specifies to annul the unprotected instruction; and
when the mode change instruction specifies to annul the unprotected instruction, cause the instruction execution pipeline to annul the unprotected instruction by completing the unprotected instruction to produce a result and discarding the result.