CPC G06F 9/3016 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01); G06F 16/9017 (2019.01); G06F 9/3012 (2013.01); G06F 9/30141 (2013.01); G06F 9/355 (2013.01); G06F 9/383 (2013.01); G06F 12/0292 (2013.01)] | 21 Claims |
1. A processor comprising:
a first memory configured to store instructions, wherein each instruction includes a data processing operation and at least one data operand field;
a second memory configured to store a set of tables; and
at least one functional unit coupled to the second memory,
wherein the at least one functional unit is configured to:
based on a table read instruction,
recall, based on a look up table enable register, a set of data elements that includes a respective element from each one of the set of tables at a respective address, wherein the look up table enable register specifies whether recall of the data element from each one of the set of tables is permitted;
generate, based on a look up table configuration register, a number of equally sized extensions for each element of the set of data elements, wherein the look up table configuration register specifies a promotion mode representing the number of equally sized extensions for the respective element of the set of data elements, wherein a Ox promotion mode represents a first number of equally sized extensions, a 2× promotion mode represents a second number of equally sized extensions, a 4× promotion mode represents a third number of equally sized extensions, and an 8× promotion mode represents a fourth number of equally sized extensions; and
store the set of data elements, wherein each element of the set of data elements is stored with the number of equally sized extensions.
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