US 12,321,748 B2
Central processing unit (CPU) instruction flow optimization based on performance-efficiency classifications for CPU instructions
Ricardo Banffy, Dublin (IE)
Assigned to HONEYWELL INTERNATIONAL INC., Charlotte, NC (US)
Filed by HONEYWELL INTERNATIONAL INC., Charlotte, NC (US)
Filed on Jul. 31, 2023, as Appl. No. 18/362,016.
Prior Publication US 2025/0045053 A1, Feb. 6, 2025
Int. Cl. G06F 9/30 (2018.01); G06F 11/34 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 11/3466 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
one or more processors;
a memory; and
one or more programs stored in the memory, the one or more programs comprising instructions configured to:
determine a performance-efficiency classification for a central processing unit (CPU) instruction based on an instruction dependency between the CPU instruction and one or more other CPU instructions, wherein the instruction dependency is based on a number of CPU instructions in an instruction workflow between the CPU instruction and the one or more other CPU instructions;
determine a particular execution unit from a set of execution units that comprises a defined performance-efficiency classification corresponding to the performance-efficiency classification associated with the CPU instruction; and
cause execution of the CPU instruction via the particular execution unit.