| CPC G06F 8/452 (2013.01) | 19 Claims |

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1. An apparatus, the apparatus comprising:
a processor configured to:
generate each of intermediate representation codes corresponding to each of a plurality of loop structures obtained that corresponds to a neural network computation based on an input specification file of hardware;
schedule instructions included in each of the intermediate representation codes corresponding to the plurality of loop structures;
select, based on latency values predicted according to scheduling results of the intermediate representation codes, any one code among the intermediate representation codes; and
allocate, based on a scheduling result of the selected intermediate representation code, instructions included in the selected intermediate representation code to resources of the hardware included in the apparatus,
wherein the plurality of loop structures is determined based on a combination of a plurality of tiling sizes and a plurality of dataflows.
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