US 12,321,714 B2
Compressed wallace trees in FMA circuits
Aditya Varma, Noida (IN); Mahesh Kumashikar, Bangalore (IN); and Michael Espig, Newberg, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,722.
Claims priority of application No. 202141021768 (IN), filed on May 14, 2021.
Prior Publication US 2022/0365751 A1, Nov. 17, 2022
Int. Cl. G06F 7/53 (2006.01); G06F 7/502 (2006.01); G06F 17/16 (2006.01)
CPC G06F 7/5318 (2013.01) [G06F 7/502 (2013.01); G06F 7/5312 (2013.01); G06F 17/16 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
two or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree comprising:
multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit; and
a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits; and
circuitry coupled to the two or more fractional width FMA circuits to provide one or more fractional width FMA operations through the two or more fractional width FMA circuits.