US 12,321,682 B2
Post-routing congestion optimization
Ching Hsu, Zhubei (TW); Heng-Yi Lin, Taichung (TW); and Yi-Lin Chuang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,567.
Application 18/447,567 is a division of application No. 17/232,491, filed on Apr. 16, 2021, granted, now 11,853,681.
Prior Publication US 2024/0126973 A1, Apr. 18, 2024
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving design rule check (DRC) violation information on a post-routing integrated circuit (IC) layout and detect cluster DRC violations including a first DRC violation in a cluster box;
generating an optimization plan based on the DRC violation information, wherein generating the optimization plan includes:
identifying a blockage area on a post-routing IC layout, a routing congestion box being located in the blockage area, a plurality of cluster DRC violations being located in the routing congestion box;
generating a detour path connecting a first endpoint and a second endpoint, the detour path surrounding the blockage area;
identifying a plurality of candidate points on the detour path;
selecting, among the plurality of candidate points, an anchor buffer such that a first fly line connecting the anchor buffer and the first endpoint and a second fly line connecting the anchor buffer and the second endpoint do not cross the routing congestion box;
storing a location of the anchor buffer; and
fixing the first DRC violation in accordance with the optimization plan.