US 12,321,681 B2
Full die and partial die tape outs from common design
Haim Hauzi, Ramat Gan (IL); Eran Tamari, Herzeliya Pituach (IL); Per H. Hammarlund, Sunnyvale, CA (US); Jonathan M. Redshaw, St Albans (GB); Alfredo Kostianovsky, Tel Aviv (IL); Idan Nissel, Petach-Tiqva (IL); Leonid Gitelman, Yokneam (IL); Oren Betzalel, Herzliya (IL); Dalia R. Haim, Haifa (IL); and Lior Zimet, Kerem Maharal (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertrino, CA (US)
Filed on Jul. 26, 2022, as Appl. No. 17/873,694.
Claims priority of provisional application 63/236,013, filed on Aug. 23, 2021.
Prior Publication US 2023/0053664 A1, Feb. 23, 2023
Int. Cl. G06F 30/398 (2020.01); G03F 1/70 (2012.01); G06F 30/392 (2020.01)
CPC G06F 30/398 (2020.01) [G03F 1/70 (2013.01); G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
defining, in a design database corresponding to an integrated circuit design, an area to be occupied by the integrated circuit design when fabricated on a semiconductor substrate;
defining a chop line that demarcates the area into a first subarea and a second subarea, wherein a combination of the first subarea and the second subarea represents a full instance of the integrated circuit, and wherein the first subarea and a stub area represents a partial instance of the integrated circuit that includes fewer circuit components than the full instance;
representing, in the design database, a physical location of a plurality of circuit components included in both the full instance and the partial instance of the integrated circuit in the first subarea, wherein a relative location of the plurality of circuit components within the first subarea and an interconnect of the plurality of circuit components within the first subarea is unchanged in the full instance and the partial instance;
representing, in the design database, a physical location of another plurality of circuit components included in the full instance but excluded from the partial instance in the second subarea;
defining, in the stub area in the design database, terminations for wires that traverse the chop line between the first and second subareas in the full instance, ensuring correct operation of the plurality of circuit components in the first subarea in the absence of the second subarea in the partial instance;
producing a first data set for the full instance using the first subarea and the second subarea, the first data set defining the full instance for manufacturing the full instance;
producing a second data set for the partial instance using the first subarea and the stub area, the second data set defining the partial instance for manufacture of the partial instance;
transmit the first data set for use in manufacturing a plurality of full instances; and
transmit the second data set for use in manufacturing a plurality of partial instances.