US 12,321,680 B2
Integrated circuit fin structure
Po-Hsiang Huang, Hsinchu (TW); Fong-Yuan Chang, Hsinchu (TW); Clement Hsingjen Wann, Hsinchu (TW); Chih-Hsin Ko, Hsinchu (TW); Sheng-Hsiung Chen, Hsinchu (TW); Li-Chun Tien, Hsinchu (TW); and Chia-Ming Hsu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/517,400.
Application 17/376,413 is a division of application No. 16/599,552, filed on Oct. 11, 2019, granted, now 11,080,453, issued on Aug. 3, 2021.
Application 18/517,400 is a continuation of application No. 18/065,275, filed on Dec. 13, 2022, granted, now 11,861,282.
Application 18/065,275 is a continuation of application No. 17/376,413, filed on Jul. 15, 2021, granted, now 11,568,122, issued on Jan. 21, 2023.
Claims priority of provisional application 62/753,259, filed on Oct. 31, 2018.
Prior Publication US 2024/0086612 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); G06F 111/20 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); G06F 2111/20 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
first through third rows of fin field-effect transistors (FinFETs), wherein
the second row is between and adjacent to each of the first and third rows,
the FinFETs of the first row are one of an n-type or p-type,
the FinFETs of the second and third rows are the other of the n-type or p-type,
the FinFETs of the first and third rows comprise a first total number of fins, and
the FinFETs of the second row comprise a second total number of fins one greater or fewer than the first total number of fins.