US 12,321,674 B2
Hierarchical CDC and RDC verification
Sudhakar Surendran, Bangalore (IN); and Venkatraman Ramakrishnan, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 31, 2022, as Appl. No. 17/589,317.
Prior Publication US 2023/0244841 A1, Aug. 3, 2023
Int. Cl. G06F 30/3312 (2020.01); G06F 115/08 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 2115/08 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, the IP cores comprising reusable units of logic for a system on a chip (SoC); and
performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, the hierarchical CDC and RDC verification including consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use of the IP cores in the SoC.