US 12,321,642 B2
Flash memory access scheduling
Sriramakrishnan Govindarajan, Bangalore (IN); Vignesh Raghavendra, Bangalore (IN); Mihir Mody, Bangalore (IN); Mohammad Asif Farooqui, Bangalore (IN); Shailesh Ghotgalkar, Bangalore (IN); and Sai Rajaraman, Frisco, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 26, 2023, as Appl. No. 18/359,729.
Prior Publication US 2025/0036315 A1, Jan. 30, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
memory access circuitry configured to:
receive a read request to obtain an instruction stored in non-volatile memory;
determine whether to preempt current access to the non-volatile memory corresponding to another access requests based on a priority of the read request relative to the other access request; and
based on a determination to preempt the current access,
pause the current access to the non-volatile memory corresponding to the other access request; and
process the read request to obtain the instruction from the non-volatile memory; and
processing circuitry coupled to the memory access circuitry and configured to execute the obtained instruction.