US 12,321,639 B2
Hybrid solid state drive (SSD) architecture using MRAM and NAND for improved power loss protection and performance
Fei Xue, Sunnyvale, CA (US); Wentao Wu, Shanghai (CN); Jiajing Jin, Hangzhou (CN); Xiang Gao, Shanghai (CN); Jifeng Wang, Chengdu (CN); Yuming Xu, Chengdu (CN); Jiu Heng, Chengdu (CN); and Hongzhong Zheng, Los Gatos, CA (US)
Assigned to Alibaba (China) Co., Ltd., Hangzhou (CN)
Filed by Alibaba (China) Co., Ltd., Hangzhou (CN)
Filed on Apr. 30, 2023, as Appl. No. 18/309,825.
Claims priority of application No. 202211234244.7 (CN), filed on Oct. 10, 2022.
Prior Publication US 2024/0118835 A1, Apr. 11, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G06F 3/0607 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A solid state drive (SSD) comprising:
a magnetoresistive random-access memory (MRAM);
a NAND memory; and
an SSD controller coupled to the MRAM and the NAND memory, wherein the SSD controller comprises:
a data allocation circuit configured to determine saving data to one of the MRAM or the NAND memory; and
an MRAM controller coupled to the MRAM and configured to read data from or write data to the MRAM,
wherein the SSD controller is configured to:
receive first data from a host machine;
save the first data to an SSD data buffer;
fetch the first data from the SSD data buffer and write the first data to the MRAM via the MRAM controller;
determine, by the data allocation circuit based on a characteristic of the first data, whether to save the first data to the MRAM or the NAND memory;
in response to determining saving the first data to the NAND memory, read the first data from the MRAM, write the first data to the NAND memory, and erase the first data from the MRAM,
wherein the data allocation circuit is further configured to:
calculate a read access frequence of a logic block in the NAND memory,
determine whether the read access frequency of the logic block exceeds a threshold frequency determined based on a storage capacity of the MRAM, wherein the threshold frequency is inversely related to the storage capacity of the MRAM, and
in response to determining the read access frequency of the logic block exceeding the threshold frequency, relocate data stored on the logic block on the NAND memory to the MRAM.