| CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] | 15 Claims |

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1. An image processing apparatus comprising:
a line buffer configured to store image data;
a clock gating circuit configured to apply a clock signal to the line buffer;
a data processor comprising a state information storage and configured to determine, when performing a write operation, whether to skip the write operation to the line buffer for each of adjacent data according to whether a value of each of the adjacent data within an image is the same,
wherein the state information storage is configured to store state information indicating whether the write operation of data at each address is skipped and comprises a scoreboard having the same number of bits as a number of addresses in the line buffer; and
a scoreboard enable controller configured to control an enable state of the scoreboard based on a number of occurrences of adjacent identical data within a range of a specified unit,
wherein the data processor is further configured to control the clock gating circuit, such that the clock signal is not applied to the line buffer while the write operation is skipped and the clock signal is applied to the line buffer while the write operation is performed,
wherein the scoreboard enable controller is configured to:
count the number of occurrences of the adjacent identical data that is less than a required minimum number of the adjacent identical data, when the scoreboard is enabled,
keep the scoreboard enabled, when the counted number is less than a specified first number of acceptable threshold, and
disable the scoreboard, when the counted number is greater than or equal to the specified first number of acceptable threshold.
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