US 12,321,631 B2
Suspension during a multi-plane write procedure
Caixia Yang, Boise, ID (US); and Deping He, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2024, as Appl. No. 18/417,808.
Application 18/417,808 is a continuation of application No. 17/654,552, filed on Mar. 11, 2022, granted, now 11,899,963.
Prior Publication US 2024/0241663 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0676 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising: one or more memory devices; and one or more memory controllers coupled with the one or more memory devices, the one or more memory controllers configured to cause the apparatus to: determine, during a multi-plane write procedure for writing data to a set of planes, that a first plane of the set of planes is defective; write, based at least in part on the first plane being defective, a remainder of the data to one or more of a remainder of the set of planes that excludes the first plane, the remainder of the data excluding a first subset of the data; and delay, based at least in part on the first plane being defective, writing the first subset of the data to the first plane until the remainder of the data is written to the one or more of the remainder of the set of planes.