US 12,321,622 B2
Deferred ECC (error checking and correction) memory initialization by memory scrub hardware
Sreenivas Mandava, Los Altos, CA (US); and John V. Lovelace, Driftwood, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,960.
Prior Publication US 2021/0382640 A1, Dec. 9, 2021
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array having an address range; and
an error scrubbing engine coupled to the memory array, the error scrubbing engine to:
initialize a first portion of the memory array and indicate that the first portion is initialized prior to initializing a second portion of the memory array, wherein during initialization of the first portion, the error scrubbing engine is to generate write transactions limited by a first initialization credit;
initialize the second portion of the memory array after a BIOS (basic input/output system) is loaded into the initialized first portion the memory array, wherein during initialization of the second portion, the error scrubbing engine is to generate write transactions limited by a second initialization credit that is lower than the first initialization credit; and
perform scrub operations on the memory array during runtime, after the first portion and the second portion are initialized, wherein during runtime, the error scrubbing engine is to generate write transactions limited by a runtime credit that is lower than the second initialization credit.