| CPC G06F 3/0619 (2013.01) [G06F 3/0644 (2013.01); G06F 3/0673 (2013.01); G06F 11/1068 (2013.01)] | 20 Claims |
|
1. A method of operating a memory system including a memory device and a memory controller, the method comprising:
programming, by the memory device, K logical pages stored in a page buffer circuit into a memory cell array to set a threshold voltage distribution for the memory cell array;
reading, by the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses;
correcting, by the memory controller, errors in the read K logical pages to generate error-corrected K logical pages;
transmitting, by the memory controller, N−K logical pages to the memory device;
combining the error-corrected K logical pages and the N−K logical pages to generate N logical pages;
programming, by the memory device, the N logical pages into the memory cell array to adjust the threshold voltage distribution,
wherein K is a positive integer and N is a positive integer greater than K.
|