US 12,321,608 B2
Read cache memory
Eugene Feng, San Jose, CA (US); and Mathew Arcoleo, Campbell, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 6, 2020, as Appl. No. 16/987,055.
Application 16/987,055 is a division of application No. 15/619,966, filed on Jun. 12, 2017, granted, now 10,768,828.
Application 15/619,966 is a division of application No. 14/282,467, filed on May 20, 2014, granted, now 9,710,173, issued on Jul. 18, 2017.
Prior Publication US 2020/0363962 A1, Nov. 19, 2020
Int. Cl. G06F 3/06 (2006.01); G06F 12/0806 (2016.01); G06F 12/0875 (2016.01); G06F 12/0888 (2016.01); G06F 12/1081 (2016.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01); G11C 29/44 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0655 (2013.01); G06F 3/0685 (2013.01); G06F 3/0688 (2013.01); G06F 12/0806 (2013.01); G06F 12/0875 (2013.01); G06F 12/0888 (2013.01); G06F 12/1081 (2013.01); G06F 13/28 (2013.01); G11C 7/1072 (2013.01); G11C 29/44 (2013.01); G11C 29/765 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/621 (2013.01); G11C 2029/0409 (2013.01); G11C 2207/2245 (2013.01); Y02D 10/00 (2018.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a substrate;
a dynamic random-access memory (DRAM) array formed on a first die coupled to the substrate;
a NAND array formed on a second die coupled to the first die in a first offset manner;
a controller formed on a third die coupled to the second die via direct die-to-die bonding; and
a fan-out wafer level packaging (WLP) pad adjacent to the controller, wherein the controller is coupled to the DRAM array via the WLP pad and a first bonding wire and coupled to the NAND array via the WLP pad and a second bonding wire, and wherein data is moved from the DRAM array to the NAND array via the WLP pad, the first bonding wire, and the second bonding wire.