| CPC G06F 3/0614 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] | 18 Claims |
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1. A memory device, comprising:
a plurality of channel layers;
a plurality of word lines;
a plurality of memory layers disposed between the channel layers and the word lines; and
a plurality of memory cells defined at cross-points of the channel layers and the word lines;
wherein the memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n, wherein in the first operation, a first electric field is produced in a portion of the memory layers, and wherein the word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field,
wherein in the second operation, the second electric field is produced by a first voltage applied to one of the word lines that corresponds to the portion of the memory layers and a second voltage applied to another one of the word lines that corresponds the portion.
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