US 12,321,440 B2
Control device and program verification method
Nobuyoshi Morita, Tokyo (JP); Yasuhiro Fujii, Tokyo (JP); Mikio Kataoka, Tokyo (JP); and Masashi Yano, Tokyo (JP)
Assigned to Hitachi Astemo, Ltd., Hitachinaka (JP)
Appl. No. 17/924,571
Filed by Hitachi Astemo, Ltd., Hitachinaka (JP)
PCT Filed Feb. 25, 2021, PCT No. PCT/JP2021/007123
§ 371(c)(1), (2) Date Nov. 10, 2022,
PCT Pub. No. WO2022/009464, PCT Pub. Date Jan. 13, 2022.
Claims priority of application No. 2020-117468 (JP), filed on Jul. 8, 2020.
Prior Publication US 2023/0147082 A1, May 11, 2023
Int. Cl. G06F 21/44 (2013.01); G06F 21/57 (2013.01); H04L 9/14 (2006.01)
CPC G06F 21/44 (2013.01) [G06F 21/57 (2013.01); H04L 9/14 (2013.01); G06F 2221/033 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A control device comprising at least one processor and memory, to:
store at least a program to be verified, a plurality of verification expected values related to verification of the program, and information comprising an address for identifying one of the plurality of verification expected values,
identify a verification expected value from the plurality of verification expected values based on the address,
generate a verification value by executing an encryption processing operation using a predetermined key value and the program to be verified as inputs,
verify whether the program is correct based on a comparison between verification value and the identified verification expected value, and
execute the program in response to verifying that the program is correct.