US 12,321,310 B2
Implicit fence for write messages
Joydeep Ray, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); Varghese George, Folsom, CA (US); Mike Macpherson, Portland, OR (US); Aravindh Anantaraman, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Nicolas Galoppo von Borries, Portland, OR (US); and Ben J. Ashbaugh, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 20, 2023, as Appl. No. 18/491,474.
Application 18/491,474 is a continuation of application No. 17/849,201, filed on Jun. 24, 2022, granted, now 11,899,614.
Application 17/849,201 is a continuation in part of application No. 17/428,530, granted, now 12,210,477, previously published as PCT/US2020/022837, filed on Mar. 14, 2020.
Claims priority of provisional application 62/819,337, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,435, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,361, filed on Mar. 15, 2019.
Prior Publication US 2024/0086356 A1, Mar. 14, 2024
Int. Cl. G06F 15/78 (2006.01); G06F 7/544 (2006.01); G06F 7/575 (2006.01); G06F 7/58 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/0866 (2016.01); G06F 12/0871 (2016.01); G06F 12/0875 (2016.01); G06F 12/0882 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/0893 (2016.01); G06F 12/0895 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 12/128 (2016.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06F 17/18 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); H03M 7/46 (2006.01); G06N 3/08 (2023.01); G06T 15/06 (2011.01)
CPC G06F 15/7839 (2013.01) [G06F 7/5443 (2013.01); G06F 7/575 (2013.01); G06F 7/588 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30065 (2013.01); G06F 9/30079 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/5011 (2013.01); G06F 9/5077 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0866 (2013.01); G06F 12/0871 (2013.01); G06F 12/0875 (2013.01); G06F 12/0882 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0893 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 12/128 (2013.01); G06F 15/8046 (2013.01); G06F 17/16 (2013.01); G06F 17/18 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); H03M 7/46 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3867 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/302 (2013.01); G06F 2212/401 (2013.01); G06F 2212/455 (2013.01); G06F 2212/60 (2013.01); G06N 3/08 (2013.01); G06T 15/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a first cache;
a graphics core associated with the first cache, the graphics core including a processing resource and a surface state cache; and
memory access circuitry to process a memory access message received from the processing resource, the memory access circuitry including fence circuitry to order memory operations according to a fence instruction, wherein the memory access circuitry is configured to:
receive a write request message in response to execution of an instruction by the processing resource to perform a write to a memory surface;
determine a scope attribute and cache attributes associated with the write request message including to determine a first cache attribute based on a request descriptor associated with the write request message and determine a second cache attribute based on state information associated with the memory surface within the surface state cache;
perform a memory store operation according to the scope attribute and the cache attributes;
examine a request descriptor of the write request message for presence of an implicit fence attribute; and
request a fence operation via the fence circuitry in response to detection of the implicit fence attribute within the request descriptor, the fence operation to order a write sequence to the memory surface.