US 12,321,301 B1
Low-latency packet processing for network device
Erez Izenberg, Tel Aviv (IL); Said Bshara, Tira (IL); Jonathan Cohen, Hod Hasharon (IL); and Avigdor Segal, Netanya (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Aug. 19, 2022, as Appl. No. 17/891,200.
Application 17/891,200 is a continuation of application No. 17/203,231, filed on Mar. 16, 2021, granted, now 11,467,998.
Int. Cl. G06F 13/42 (2006.01); G06F 9/46 (2006.01); G06F 13/28 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 9/466 (2013.01); G06F 13/28 (2013.01); G06F 15/173 (2013.01); G06F 15/7807 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a device memory including a packet descriptor queue; and
detection logic for detecting data segments written to the packet descriptor queue by detecting data sizes of incoming write transactions to the packet descriptor queue;
wherein the device is configured to:
write a first set of data segments to a first entry of the packet descriptor queue, the first set of data segments corresponding to a first DMA descriptor, wherein writing the first set of data segments includes writing a first data segment having a first data size to a first address in the first entry and a second data segment having a second data size to a second address in the first entry;
write a second set of data segments to a second entry of the packet descriptor queue, the second set of data segments corresponding to a second DMA descriptor;
determine, based on a combined size including the first data size and the second data size, that the first DMA descriptor has been completely written to the first entry; and
in response to determining that the first DMA descriptor has been completely written to the first entry, and prior to a completion of writing the second set of data segments, begin processing the first DMA descriptor.