US 12,321,284 B2
Methods and apparatus to facilitate atomic operations in victim cache
Naveen Bhoria, Plano, TX (US); Timothy David Anderson, University Park, TX (US); and Pete Michael Hippleheuser, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 15, 2024, as Appl. No. 18/442,660.
Application 18/442,660 is a continuation of application No. 17/875,572, filed on Jul. 28, 2022, granted, now 11,940,930.
Application 17/875,572 is a continuation of application No. 16/882,262, filed on May 22, 2020, granted, now 11,403,229, issued on Aug. 2, 2022.
Claims priority of provisional application 62/852,494, filed on May 24, 2019.
Prior Publication US 2024/0193098 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/128 (2016.01); G06F 9/30 (2018.01); G06F 9/54 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/0804 (2016.01); G06F 12/0806 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0853 (2016.01); G06F 12/0855 (2016.01); G06F 12/0864 (2016.01); G06F 12/0884 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/0895 (2016.01); G06F 12/0897 (2016.01); G06F 12/1027 (2016.01); G06F 12/12 (2016.01); G06F 12/121 (2016.01); G06F 12/126 (2016.01); G06F 12/127 (2016.01); G06F 13/16 (2006.01); G06F 15/80 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G06F 12/128 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/546 (2013.01); G06F 11/1064 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0292 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0806 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/082 (2013.01); G06F 12/0853 (2013.01); G06F 12/0855 (2013.01); G06F 12/0864 (2013.01); G06F 12/0884 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/1027 (2013.01); G06F 12/12 (2013.01); G06F 12/121 (2013.01); G06F 12/126 (2013.01); G06F 12/127 (2013.01); G06F 13/1605 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 15/8069 (2013.01); G11C 5/066 (2013.01); G11C 7/10 (2013.01); G11C 7/1015 (2013.01); G11C 7/106 (2013.01); G11C 7/1075 (2013.01); G11C 7/1078 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/301 (2013.01); G06F 2212/454 (2013.01); G06F 2212/603 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/6042 (2013.01); G06F 2212/608 (2013.01); G06F 2212/62 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a cache memory configured to store data;
a cache store queue coupled to the cache memory, the cache store queue including an arithmetic unit; and
a cache controller coupled to the cache memory and the cache store queue, the cache controller configured to:
receive a histogram operation directed to the data; and
cause the arithmetic unit to:
receive the data from the cache memory; and
generate a histogram based on incrementing respective values of a vector based on occurrence of respective unique values in the data.