US 12,321,282 B2
Slot/sub-slot prefetch architecture for multiple memory requestors
Kai Chirca, Richardson, TX (US); Joseph R. M. Zbiciak, San Jose, CA (US); and Matthew D. Pierson, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 7, 2023, as Appl. No. 18/463,101.
Application 18/463,101 is a continuation of application No. 17/384,864, filed on Jul. 26, 2021, granted, now 11,789,872, issued on Oct. 17, 2023.
Application 17/384,864 is a continuation of application No. 16/552,418, filed on Aug. 27, 2019, granted, now 11,074,190, issued on Jul. 27, 2021.
Application 16/552,418 is a continuation of application No. 15/899,138, filed on Feb. 19, 2018, granted, now 10,394,718, issued on Aug. 27, 2019.
Application 15/899,138 is a continuation of application No. 13/233,443, filed on Sep. 15, 2011, granted, now 9,898,415, issued on Feb. 20, 2018.
Claims priority of provisional application 61/387,367, filed on Sep. 28, 2010.
Claims priority of provisional application 61/384,932, filed on Sep. 21, 2010.
Prior Publication US 2023/0418759 A1, Dec. 28, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/0897 (2016.01); G06F 9/38 (2018.01); G06F 12/0886 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 9/3802 (2013.01); G06F 9/3806 (2013.01); G06F 9/3844 (2013.01); G06F 12/0886 (2013.01); G06F 2212/602 (2013.01); G06F 2212/6022 (2013.01); G06F 2212/6028 (2013.01); Y02D 10/00 (2018.01)] 12 Claims
OG exemplary drawing
 
1. A device comprising:
multiple memories; and
a memory controller coupled to the multiple memories, the memory controller including:
a prefetch stream filter that includes a first set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots of the first set of address slots; and
a prefetch buffer that includes a set of buffer slots, each slot of the set of buffer slots including an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots configured to store data, wherein each address field of each slot of the set of buffer slots is configured to store at least a portion of an address associated with the corresponding slot.