US 12,321,279 B2
Multi-port queueing cache and data processing system including the same
Heonsoo Lee, Suwon-si (KR); Byungchul Hong, Suwon-si (KR); Junseok Park, Suwon-si (KR); and Jaehun Chung, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 3, 2024, as Appl. No. 18/654,803.
Application 18/654,803 is a continuation of application No. 18/072,929, filed on Dec. 1, 2022, granted, now 12,013,786.
Claims priority of application No. 10-2021-0185205 (KR), filed on Dec. 22, 2021; and application No. 10-2022-0062093 (KR), filed on May 20, 2022.
Prior Publication US 2024/0289278 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0862 (2016.01); G06F 9/38 (2018.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01)
CPC G06F 12/0862 (2013.01) [G06F 9/3816 (2013.01); G06F 12/0261 (2013.01); G06F 12/0646 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system comprising:
a data processing device;
a memory device configured to store a plurality of data used for calculations performed by the data processing device; and
a first multi-port queueing cache between the data processing device and the memory device,
a second multi-port queueing cache between the data processing device and the memory device,
wherein the first multi-port queueing cache includes:
a plurality of first ports and a plurality of second ports;
a plurality of first request handlers configured to receive a plurality of first addresses and output a plurality of first data through the plurality of first ports;
a first cache storage including a plurality of first cache lines, and configured to output at least a portion of the plurality of first addresses and receive at least a portion of the plurality of first data through the plurality of second ports;
a first reserve interface and a first request interface disposed between the plurality of first request handlers and the first cache storage, and configured to exchange at least one address, at least one reserved cache line number and at least one data.