	US 12,321,271 B2
	Distributed system level cache
Mark Landers, Hartwell (GB); Ian King, Hertfordshire (GB); Alistair Goudie, Hertfordshire (GB); and Michael John Livesley, Hertfordshire (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Sep. 29, 2023, as Appl. No. 18/374,821.
Claims priority of application No. 2214307 (GB), filed on Sep. 29, 2022.
Prior Publication US 2024/0160571 A1, May 16, 2024
Int. Cl. G06F 12/0811 (2016.01); G06F 12/0877 (2016.01)

CPC G06F 12/0811 (2013.01) [G06F 12/0877 (2013.01)]

20 Claims

1. A processor, comprising:

a plurality of cores comprising a first core and a second core;

a distributed cache comprising a plurality of cache slices including a first cache slice and a second cache slice; and

a first interconnect between the first cache slice and the second cache slice;

wherein the distributed cache is configured to cache a copy of data stored at a plurality of memory addresses of a memory;

wherein the first cache slice is connected to the first core, and the second cache slice is connected to the second core;

wherein the first cache slice is configured to cache a copy of data stored at a first set of memory addresses of the plurality of memory addresses;

wherein the second cache slice is configured to cache a copy of data stored at a second, different, set of memory addresses of the plurality of memory addresses;

wherein the first cache slice is configured to:

receive, from the first core, a first memory access request specifying a target memory address of the memory, wherein the plurality of memory addresses includes the first target memory address,

identify based on the target memory address a target cache slice among the first and second cache slices, wherein the target cache slice is the cache slice configured to cache a copy of the data stored at the target memory address, and

responsive to the target cache slice being identified as the second cache slice, forward the first memory access request to the target cache slice;

wherein the first interconnect is configured to convey the first memory access request to the second cache slice;

wherein the first cache slice comprises a first cache bank configured to cache the copy of the data stored at the first set of memory addresses, and a first crossbar connected to the first cache bank;

wherein the second cache slice comprises a second cache bank configured to cache the copy of the data stored at the second set of memory addresses, and a second crossbar connected to the second cache bank;

wherein the first crossbar is configured to:

receive, from the first core, the first memory access request,

identify based on the target memory address a target cache bank among the first and second cache banks, wherein the target cache bank is the cache bank configured to cache the copy of the data stored at the target memory address, and

forward the first memory access request to the target cache bank; and

wherein the first interconnect is configured to convey the first memory access request to the second crossbar when the target cache bank is identified as the second cache bank.