US 12,321,247 B2
Multi-core processor debugging systems and methods
Arjun Chaudhuri, Hangzhou (CN); and Chunsheng Liu, Hangzhou (CN)
Assigned to T-Head (Shanghai) Semiconductor Co., Ltd., Shanghai Free Trade Area (CN)
Filed by T-Head (Shanghai) Semiconductor Co., Ltd., Shanghai Free Trade Area (CN)
Filed on Mar. 26, 2020, as Appl. No. 16/831,329.
Prior Publication US 2024/0338288 A1, Oct. 10, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/22 (2006.01)
CPC G06F 11/2242 (2013.01) 21 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of processing cores configured to process information, wherein the plurality of processing cores are configured to perform respective test operations within respective ones of the plurality of processing cores, wherein the plurality of processing cores are organized in a hierarchy of debug clusters;
a test result compaction component configured to compact results of the respective test operations from a portion of the plurality of processing cores, wherein a compacted indication of a passing test result and failed test result are available at a debug cluster basis, wherein the test result compaction component comprises logic gates; and
a non-intuitive debug component coupled to the test result compaction component, wherein the non-intuitive debug component is configured to resolve the failed test result available at the debug cluster basis by identifying a member within a debug cluster that is associated with a respective one of the plurality of processing cores that has a fault, wherein the non-intuitive debug component comprises logic gates, wherein respective ones of the plurality of processing cores that are identified as having a fault are adjusted to mitigate impacts associated with the fault, wherein tests results of the respective members within a respective debug cluster are logically ORed together and the output of the logical ORing indicates whether or not members in the respective debug cluster pass the test.