US 12,321,234 B2
Energy efficient storage of error-correction-detection information
Michael Raymond Miller, Raleigh, NC (US); Stephen Magee, Apex, NC (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 29, 2024, as Appl. No. 18/649,031.
Application 18/649,031 is a continuation of application No. 18/130,810, filed on Apr. 4, 2023, granted, now 12,001,283.
Application 18/130,810 is a continuation of application No. 17/734,464, filed on May 2, 2022, granted, now 11,645,152, issued on May 9, 2023.
Application 17/734,464 is a continuation of application No. 16/881,859, filed on May 22, 2020, granted, now 11,347,587, issued on May 31, 2022.
Application 16/881,859 is a continuation of application No. 15/990,078, filed on May 25, 2018, granted, now 10,705,912, issued on Jul. 7, 2020.
Claims priority of provisional application 62/516,240, filed on Jun. 7, 2017.
Prior Publication US 2024/0354191 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 3/0644 (2013.01); G06F 3/0673 (2013.01); G06F 11/1048 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller, comprising:
at least three memory channel interfaces that are to operate independently of accesses that occur via the other of the at least three memory channel interfaces, the at least three memory channel interfaces including a first memory channel interface, a second memory channel interface, and an error detection and correction channel interface, the first memory channel interface to access a first data word group that is stored contiguously in a first row of a first memory device coupled to the first memory channel interface concurrently with the error detection and correction channel interface accessing a first set of check bits associated with the first data word group and a second set of check bits associated with a second data word group that is stored contiguously in a second row of a second memory device coupled to the second memory channel interface; and
an error detection and correction data cache to cache the second set of check bits that was accessed concurrently with the first data word group.