US 12,321,232 B2
Memory controller which implements partial writes with error signaling
Martin Mienkina, Bystrice Nad Olsi (CZ); Quyen Pho, Pflugerville, TX (US); and Avni Arora, Delhi (IN)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Oct. 4, 2023, as Appl. No. 18/480,992.
Claims priority of application No. 202311031537 (IN), filed on May 3, 2023.
Prior Publication US 2024/0370334 A1, Nov. 7, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 13/16 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0787 (2013.01); G06F 13/1673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system, comprising:
a system interconnect;
a requestor coupled to the system interconnect and configured to provide read access requests, full write access requests with corresponding full write data each having a full-width data size, and partial write access requests with corresponding partial write data each having a partial-width data size, smaller than the full-width data size, onto the system interconnect; and
a memory comprising:
a memory array configured to store write data and corresponding error correction code (ECC) check bits for the write data in response to write access requests and to provide read data and corresponding ECC check bits for the read data in response to read access requests;
a store buffer, external to the memory array; and
a memory controller configured to execute a read-modify-write (RMW) sequence between the store buffer and the memory array to implement a partial write transaction in response to a partial write access request, wherein the memory controller is configured to store the partial write data into the store buffer upon receiving the partial write access request and suppress signaling of ECC errors to the requestor during the RMW sequence.