US 12,321,230 B2
Alias-free tagged error correcting codes for machine memory operations
Michael B Sullivan, Austin, TX (US); Mohamed Tarek Bnziad Mohamed Hassan, Lowell, MA (US); and Aamer Jaleel, Northborough, MA (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Oct. 11, 2023, as Appl. No. 18/485,132.
Claims priority of provisional application 63/386,121, filed on Dec. 5, 2022.
Prior Publication US 2024/0184670 A1, Jun. 6, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1044 (2013.01) 23 Claims
OG exemplary drawing
 
1. A device comprising:
a first memory;
decoding logic configured to operate on codewords stored in the first memory, the decoding logic comprising a second memory configured with a tag matrix comprising all-even-weight columns and a parity-check matrix comprising all-odd-weight columns.