US 12,321,214 B2
Fast self-refresh exit power state
Christopher P. Mozak, Portland, OR (US); Robert J. Royer, Jr., Portland, OR (US); Aaron Martin, El Dorado Hills, CA (US); Alex P. Thomas, El Dorado Hills, CA (US); Tomer Levy, Tel Aviv (IL); and Noam Lupovich, Pardesiya (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,651.
Prior Publication US 2022/0121263 A1, Apr. 21, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3237 (2019.01)
CPC G06F 1/3237 (2013.01) [G06F 1/3275 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a high speed clock path of a physical interface (PHY) to a memory device, the high speed clock path including frequency and phase hardware to generate a high speed clock signal, wherein the high speed clock path is to be powered down when the memory device is in self-refresh;
a reference clock path of the PHY to bypass the high speed clock path with a reference clock separate from the high speed clock signal; and
a transmitter of the PHY to drive a self-refresh exit (SRX) command to the memory device based on the reference clock to trigger the memory device to exit from self-refresh;
wherein the high speed clock path is to initiate power up in conjunction with the SRX command triggering the memory device to exit from self-refresh; and
wherein the transmitter is to transmit a subsequent command to the memory device based on the high speed clock signal after the high speed clock path is powered up.