US 12,321,025 B2
Integrated silicon photonics transceivers enabling ultra-high-speed high dense input/output and interconnect for Terabyte per second optical interconnect
Jianying Zhou, Dublin, CA (US); and Jin Hong, Saratoga, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,538.
Claims priority of provisional application 63/219,764, filed on Jul. 8, 2021.
Prior Publication US 2022/0003948 A1, Jan. 6, 2022
Int. Cl. G02B 6/42 (2006.01); G02B 6/12 (2006.01); G02F 1/03 (2006.01); G02F 1/21 (2006.01); G02F 1/225 (2006.01)
CPC G02B 6/4279 (2013.01) [G02B 6/12004 (2013.01); G02B 6/4215 (2013.01); G02F 1/0316 (2013.01); G02F 1/212 (2021.01); G02F 1/2255 (2013.01); G02F 2201/127 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a photonic integrated circuit (PIC) on a first semiconductor die having a first side and a second side opposite the first side, wherein the first side includes a first optical circuit and a second optical circuit and the second side is to electrically couple with a substrate, wherein the first optical circuit comprises:
a traveling wave Mach Zehnder modulator (TW MZM) comprising a 2D array of pads including a first row comprising an adjacent pair of RF input pads between two RF ground pads and including a second row of RF ground pads;
a pair of signal lines extending away from a first side of the 2D array of pads along opposite sides of a pair of adjacent optical waveguides, and coupled to the adjacent pair of RF input pads to receive and propagate an RF traveling wave;
an optical splitter on a second, opposite, side of the 2D array of pads to receive an optical input signal and output a pair of optical signals to the pair of adjacent optical waveguides under the RF traveling wave; and
an RF termination and bias circuit coupled to an opposite end of the pair of signal lines and comprising a first RF ground capacitor integrated into the PIC, the first RF ground capacitor to couple in parallel with a second, larger, capacitor, external to the PIC;
a driver on a second semiconductor die, wherein a corresponding 2D array of pads of the driver are flip chip bonded to the 2D array of pads of the TW MZM; and
an application specific integrated circuit (ASIC) on a third semiconductor die, wherein the ASIC comprises:
a digital signal processor to output first digital data and receive second digital data;
a digital-to-analog converter to convert the first digital data to first analog data, the digital-to-analog converter to couple to the driver through silicon vias (TSVs) in the first semiconductor die.