US 12,320,903 B2
Multiple and cascaded redundant disciplined oscillator systems in a spoofing resistant reference time source system and methods thereof
David Sohn, Pittsford, NY (US); John Fischer, Corfu, NY (US); and Matthias Lorentz, Choisel (FR)
Assigned to Orolia USA Inc., West Henrietta, NY (US)
Filed by Orolia USA Inc., W. Henrietta, NY (US)
Filed on Oct. 28, 2022, as Appl. No. 17/975,935.
Application 17/975,935 is a continuation in part of application No. 17/374,465, filed on Jul. 13, 2021, granted, now 12,019,166.
Prior Publication US 2023/0046689 A1, Feb. 16, 2023
Int. Cl. G01S 19/21 (2010.01); G01S 19/23 (2010.01); H04B 17/29 (2015.01)
CPC G01S 19/215 (2013.01) [G01S 19/23 (2013.01); H04B 17/29 (2015.01)] 18 Claims
OG exemplary drawing
 
1. A spoofing resistant reference time source system comprising:
an oscillator system comprising three or more redundant oscillators and a cascaded oscillator coupled to a switching system and an oscillator management computing device;
the oscillator management computing device comprising a memory coupled to a processor which is configured to execute programmed instructions stored in the memory to:
enter the three or more redundant oscillators and the cascaded oscillator into an initialization state:
discipline all but one of the redundant oscillators to a time and frequency external input into normal disciplining steady state with the remaining one of the redundant oscillators in a holdover state;
when the all but one of the redundant oscillators have reached the normal disciplining steady state, place the all but one of the redundant oscillators into the holdover state, discipline the remaining one of the redundant oscillators to the time and frequency external input, and discipline the cascaded oscillator to one of the all but one of the redundant oscillators now in the holdover state; and
when the remaining one of the redundant oscillators and the cascaded oscillator have reached the normal disciplining steady state, transition from an initialization stage to a steady state management stage.