US 12,320,847 B2
Test device for testing on-chip clock controller having debug function
Sheng-Ping Yung, Hsinchu (TW); and Pei-Ying Hsueh, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Oct. 13, 2023, as Appl. No. 18/379,686.
Claims priority of application No. 111140526 (TW), filed on Oct. 25, 2022.
Prior Publication US 2024/0133950 A1, Apr. 25, 2024
Prior Publication US 2024/0230757 A9, Jul. 11, 2024
Int. Cl. G01R 31/317 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/31727 (2013.01) [G01R 31/318552 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A test device for testing an on-chip clock controller, the test device comprising:
a scan chain including N flip-flop circuit(s) from a first flip-flop circuit to an Nth flip-flop circuit in sequence, wherein the N is a positive integer, a Kth flip-flop circuit is one of the N flip-flop circuit(s), K is a positive integer less than or equal to the N, and the Kth flip-flop circuit of the N flip-flop circuit(s) includes:
a kth input switch configured to output one of a first input signal and a second input signal as an input signal according to a scan enable (SEN) signal; and
a Kth flip-flop configured to store the input signal and output a stored signal as a Kth output signal according to an input clock, wherein the stored signal is one of the first input signal and the second input signal; and
a test circuit including:
N selective circuit(s) coupled with the N flip-flop circuit(s) respectively, wherein the N selective circuit(s) include a first selective circuit to an Nth selective circuit in sequence and corresponding to the N flip-flop circuit(s) respectively, so that a Kth selective circuit of the N selective circuit(s) corresponds to the Kth flip-flop circuit and the Kth selective circuit includes:
a Kth clock switch configured to output one of a Kth observation clock and an independent clock as the input clock for the Kth flip-flop according to a selection signal, wherein in a debug circuit test mode, the selection signal is determined according to the SEN signal and the Kth observation clock is from a Kth on-chip clocking circuit (OCC) of the on-chip clock controller,
wherein the Kth input switch outputs the first input signal according to a first signal value of the SEN signal first to let the Kth flip-flop store the first input signal according to the input clock while a value of the first input signal is a first input value; then the Kth input switch outputs the second input signal according to a second signal value of the SEN signal, and the Kth flip-flop replaces the first input signal with the second input signal or keeps the first input signal according to the input clock while a value of the second input signal is a second input value that is different from the first input value; and then the Kth output signal of the Kth flip-flop indicates whether the input clock triggers the Kth flip-flop under test setting and thereby shows whether circuit(s) under test (CUT(s)) for transmission of the input clock function(s) normally.