US 11,997,853 B1
1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 10, 2022, as Appl. No. 17/654,379.
Application 17/654,379 is a continuation of application No. 17/653,811, filed on Mar. 7, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 23 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; and
a plurality of capacitors having a first terminal coupled to the storage node via a metal layer, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors that are arranged in a staggered configuration on the metal layer such that a first capacitor of the plurality of capacitors is offset along a horizontal plane diagonally from a second capacitor of the plurality of capacitors.